Signal receiving circuit and digital signal processing system

ABSTRACT

A signal receiving circuit comprising a first P-channel MOSFET amplifier and a first N-channel MOSFET amplifier having gates supplied with positive signals from a pair of signal transmission lines; and a second P-channel MOSFET amplifier and a second N-channel MOSFET amplifier having gates supplied with negative signals from said pair of signal transmission lines; wherein a first output signal is formed by so adjusting the gains of the first P-channel MOSFET amplifier and of the second N-channel MOSFET amplifier that the resultant signals have an intermediate amplitude between the operation voltages, and a second output signal is formed by so adjusting the gains of the second P-channel MOSFET amplifier and of the first N-channel MOSFET amplifier that the resultant signals have an intermediate amplitude between the operation voltages. This makes it possible to receive various small signals lying over a wide range even by using a sense amplifier which has only a fixed operation range in the signal receiving circuit as well as to constitute a novel and optimum system by combining semiconductor integrated circuit devices having different low-amplitude interfaces.

TECHNICAL FIELD

The present invention relates to a signal receiving circuit and to adigital signal processing system and, particularly, to technology thatcan be effectively utilized for transferring signals betweensemiconductor integrated circuit devices having different operationvoltages and different types of internal logic circuits.

BACKGROUND ART

In some digital integrated circuits, small signals such as of the ECLlevel are transmitted based upon a power source voltage VCC such as GTL(gunning transceiver logic) or +5 V in order to transmit signals at highspeeds over a signal transmission line and to decrease the consumptionof electric power. The GTL has been disclosed in ISSCC, InternationalSolid State Circuit Conference, Feb. 19, 1992, pp. 58-59.

DISCLOSURE OF THE INVENTION

As described above, there are various kinds of low-amplitude interfaceshaving their own features. Therefore, they will never be uniformalizedinto a single kind of low-amplitude interface but rather it is quiteprobable that new amplitude interfaces will be developed in the future.Under such circumstances where there exist various kinds oflow-amplitude interfaces being mixed together, it becomes necessary todesign receiving circuits of semiconductor integrated circuit devices tomeet the interfaces. The present inventors therefore have devised asignal receiving circuit that can be adapted to various kinds oflow-amplitude interfaces to constitute an optimum system which includessemiconductor integrated circuit devices having various interfaces in amixed manner.

The object of the present invention therefore is to provide a signalreceiving circuit capable of being adapted to various kinds oflow-amplitude interfaces as well as to provide a novel digital signalprocessing system which permits the inclusion of various kinds oflow-amplitude interfaces.

The above-mentioned and other objects as well as novel features of thepresent invention will become obvious from the description of thespecification and the accompanying drawings.

Among the inventions disclosed in this application, a representativeexample will now be briefly described below. That is, the inventionemploys a first P-channel MOSFET amplifier and a first N-channel MOSFETamplifier having gates supplied with positive signals from a pair ofsignal transmission lines, and a second P-channel MOSFET amplifier and asecond N-channel MOSFET amplifier having gates supplied with negativesignals from said pair of signal transmission lines, and forms a firstoutput signal is formed by so adjusting the gains of the first P-channelMOSFET amplifier and of the second N-channel MOSFET amplifier that theresultant signals have an intermediate amplitude between the operationvoltages, and forms a second output signal by so adjusting the gains ofthe second P-channel MOSFET amplifier and of the first N-channel MOSFETamplifier that the resultant signals have an intermediate amplitudebetween the operation voltages, making it possible to receive varioussmall signals lying over a wide range even by using a sense amplifierwhich has only a fixed operation range based upon the level-shiftingactions of only said two MOSFET amplifiers and load MOSFETs.

Moreover, complementary digital output signals having different levelsare sent onto a pair of first and second signal transmission lines andare received by a first (second) receiving circuit which comprises afirst (third) P-channel MOSFET amplifier and a first (third) N-channelMOSFET amplifier having gates supplied with positive signals; a second(fourth) P-channel MOSFET amplifier and a second (fourth) N-channelMOSFET amplifier having gate supplied with negative signals, said first(second) receiving circuit forming a first (third) output signal by soadjusting the gains of the first (third) P-channel MOSFET amplifier andof the second (fourth) N-channel MOSFET amplifier that the resultantsignals have an intermediate amplitude between the operation voltagesand forming a second (fourth) output signal by so adjusting the gains ofsaid second (fourth) P-channel MOSFET amplifier and a first (third)N-channel MOSFET amplifier that the resultant signals have anintermediate amplitude between the operation voltages, making itpossible to constitute a novel and optimum system by combiningsemiconductor integrated circuit devices having different low-amplitudeinterfaces.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram illustrating an embodiment of a preferredlevel-shifting circuit used for a signal receiving circuit of thepresent invention;

FIG. 2 is a diagram illustrating another embodiment of the preferredlevel-shifting circuit used for the signal receiving circuit of thepresent invention;

FIG. 3 is a diagram of input/output characteristics for explaining thelevel-shifting circuit according to the present invention;

FIG. 4 is a diagram of level settings for explaining a low-amplitudeinterface to which the present invention can be adapted;

FIG. 5 is a partial block diagram illustrating an embodiment of apreferred digital signal processor of the present invention;

FIG. 6 is a diagram of waveforms for explaining the operation of thecircuit of the embodiment shown in FIG. 5;

FIG. 7 is a block diagram schematically illustrating an embodiment of apreferred digital data processing system according to the presentinvention; and

FIG. 8 is a circuit diagram illustrating another embodiment of apreferred sense amplifier used for the signal receiving circuit of thepresent invention.

BEST MODE FOR CARRYING OUT THE INVENTION

The invention will now be described in detail in conjunction with theaccompanying drawings.

FIG. 1 is a circuit diagram illustrating an embodiment of alevel-shifting circuit used for a signal receiving circuit of thepresent invention. In FIG. 1, the circuit elements are formed on asemiconductor substrate, such as a single-crystal silicon substrate,together with other circuits constituting a digital signal processor bya known semiconductor integrated circuit process. In FIG. 1, MOSFETmeans an insulated-gate field-effect transistor (IGFET), and a P-channelMOSFET is marked with a circle at the gate to distinguish it from anN-channel MOSFET.

Input terminals IN1 and IN2 receive complementary digital signalsconsisting of a positive signal and a negative signal of a smallamplitude. One input terminal IN1 is connected to the gate of aP-channel MOSFET amplifier Q1 and to the gate of an N-channel MOSFETamplifier Q5. The other input terminal IN2 is connected to the gate of aP-channel MOSFET amplifier Q2 and to the gate of an N-channel MOSFETamplifier Q6. The P-channel MOSFET amplifiers Q1 and Q2 have sources incommon and are connected in a differential manner and are furtherprovided at the drains thereof with N-channel load MOSFETs Q3 and Q4.

With their gates kept at a power-source voltage VDD, these load MOSFETsQ3 and Q4 work as resistor elements. The N-channel MOSFET amplifiers Q5and Q6 are connected at the drains thereof to the sources of theP-channel MOSFET amplifiers Q1 and Q2, and are provided at the sourcesthereof with P-channel load MOSFETs Q7 and Q8. With their gates kept ata ground potential VSS of the circuit, the load MOSFETs Q7 and Q8 serveas resistor elements.

The P-channel MOSFET amplifiers Q1, Q2 and the N-channel load MOSFETsQ3, Q4 constitute a differential amplifier circuit which inverts theinput signal. On the other hand, the N-channel MOSFET amplifiers Q5, Q6and the P-channel load MOSFETs Q7, Q8 constitute a source followeramplifier circuit. Therefore, the source of the N-channel MOSFETamplifier Q5 that forms an output signal in phase with the input signalIN1 of the positive phase, is connected in common with the drain of theP-channel MOSFET amplifier Q2 that inverts and amplifies the inputsignal IN2 of the negative phase, and produces an output signal S2.Conversely, the source of the N-channel MOSFET amplifier Q6 that formsan output signal of the same phase as the input signal IN2 of thenegative phase, is connected in common with the drain of the P-channelMOSFET amplifier Q1 that inverts and amplifies the input signal IN1 ofthe positive phase, and produces an output signal S1.

A P-channel MOSFET Q9 is connected to the junction between the commonsource and common drain of the P-channel MOSFET amplifiers Q1, Q2 and ofthe N-channel MOSFET amplifiers Q6, Q5, and the P-channel MOSFET Q9 actsas a current source with a gate connected to the ground potential VSS ofthe circuit. Similarly, an N-channel MOSFET Q10 is connected to thejunction between the common source and common drain of the N-channelload MOSFETs Q3, Q4 and of the P-channel load MOSFETs Q8, Q7, and theN-channel MOSFET Q10 acts as a current source with a gate connected tothe power source VDD.

The MOSFETs Q1 to Q10 have sizes as described below. The channel lengthsL are all equal, i.e., 0.8 μn. The P-channel MOSFET amplifiers Q1 and Q2have a channel width W which is relatively as large as 20 μn, and thecorresponding N-channel load MOSFETs Q3 and Q4 have a channel width Wwhich is relatively as small as 5 μn. Similarly, the N-channel MOSFETamplifiers Q5 and Q6 have a channel width W which is relatively as largeas 15 μn, and the corresponding P-channel load MOSFETs Q7 and Q8 have achannel width W which is relatively as small as 10 μn.

As is well known, here, when they have the same size, the N-channelMOSFETs have a large conductance. Therefore, the ratio of sizes of theP-channel load MOSFETs Q7, Q8 to the N-channel MOSFET amplifiers Q5, Q6decreases and the ratio of sizes of the N-channel load MOSFETs Q3, Q5 tothe P-channel MOSFET amplifiers Q1, Q2 increases. In terms of theconductance ratio of the load MOSFETs to the MOSFET amplifiers, however,they have nearly the same size.

The P-channel MOSFET Q9 which is a current source has a channel width of30μ and the N-channel MOSFET Q10 has a channel width of 20μ. That is,the two MOSFETs Q9 and Q10 are so formed as to flow the same current.When the N-channel MOSFET is based upon, the P-channel MOSFET has a sizewhich is about 1.5 times as great.

The ratio of sizes of the P-channel MOSFET amplifier Q1 corresponding tothe positive input IN1 to the N-channel load MOSFET Q3 is 20:5 asdescribed above, which, however, can be converted into a conductanceratio of about 20:7.5=1:0.375. The ratio of sizes of the N-channelMOSFET amplifier Q6 to the P-channel load MOSFET Q8 is 15:10 asdescribed above, which, however, can be converted into a conductanceratio of 22.5:10=1:0.444. This quite holds true even for the otheramplifier circuit corresponding to the negative input IN2.

The above-mentioned two amplifier circuits are arranged in parallel forthe output signals S1 and S2. As shown in FIG. 3 which is a diagram ofinput and output characteristics, therefore, the level can be shiftedwhile aggregating the output signals S1 and S2 within a narrow range offrom 1 V to 2.5 V even when the input signals IN1 and IN2 are smallsignals lying over a wide range of from the ground potential VSS of thecircuit to the power-source voltage VDD of about 5 V.

When the two amplifier circuits are resultant for the input signals IN1and IN2 as described above, the resultant output signals S1 and S2 arein a predetermined narrow voltage range on account of the followingreasons. When the input signals IN1 and IN2 lie in a low voltage regionsuch as of ground potential of the circuit, neither the N-channel MOSFETamplifier Q5 nor Q6 is allowed to operate or, even if they operate, thevoltage across the gate and the source is so small that the dynamicconductance of the MOSFET amplifiers is small. In this case, thegreatest voltage has been applied between the gate and the source of theP-channel MOSFET amplifiers Q1 and Q2, and a large dynamic conductanceis exhibited. Therefore, an inverting amplifier circuit made up of theP-channel MOSFET amplifiers Q1 and Q2 works dominantly for the smallsignals in a low-voltage region such as of ground potential of thecircuit, and the level of the output signal is shifted to nearly anintermediate voltage such as about 2.5 V.

On the other hand, when the input signals IN1 and IN2 lie in ahigh-voltage region such as of the power-source voltage VDD, neither theP-channel MOSFET amplifier Q1 nor Q2 operates, or even if they operate,the voltage between the gate and the source is so small that the MOSFETamplifiers exhibit a small dynamic conductance. In this case, thegreatest voltage has been applied between the gate and the source of theN-channel MOSFET amplifier Q1, and a large dynamic conductance isexhibited. Therefore, the source follower amplifier circuit made up ofthe N-channel MOSFET amplifiers Q5 and Q6 works dominantly for the smallsignals in the high-voltage region such as of the power source voltageVDD, and the levels of the output signals S1 and S2 are shifted to anintermediate voltage such as about 2.5 V in response to the conductanceratio of the load MOSFETs Q6 and Q8.

When the input signals IN1 and IN2 are nearly at the intermediatevoltage, the two amplifier circuits compensate one another to formresultant output signals S1 and S2. Therefore, the output level becomessuch that the voltage range becomes the lowest near the intermediatevoltage. As described above, even when the small input signals IN1 andIN2 lie over a wide range of from near ground potential of the circuitto the power-source voltage, the level-shifting circuit of thisembodiment exhibits a novel level-shifting function to bring the outputsignals into a narrow range of from about 1 V to about 2.5 V.

Referring to FIG. 4, the levels can be shifted to about 2 V as describedabove for a false ECL signal having a high level of 4.2 V and a lowlevel of 3.4 V, for a GTL signal having a high level of 1.2 V and a lowlevel of 0.4 V or for an ALTS signal having a high level of 4.2 V and alow level of 3.9 V proposed already by the present inventors based upona power-source voltage VDD of, for example +5 V instead of groundpotential of 0 V in the conventional circuits. The same also holds forthe signals such as LVTTL, etc.

Even when the input signals IN1, IN2 have various levels depending uponthe interfaces as described above, the output signals S1 and S2 can bewithin a predetermined voltage range. This means that the signals can bereceived by using a sense amplifier consisting of a fixed circuit whichis used for the semiconductor memories, etc. That is, there is no needto design a signal receiving circuit to meet each of the signalamplitudes in a system. Instead, the semiconductor integrated circuitdevice can be provided with a circuit for receiving various inputsignals provided the input signals are complementary signals.

FIG. 2 is a circuit diagram illustrating another embodiment of thelevel-shifting circuit used for the signal receiving circuit of thepresent invention. In this embodiment, the current source of theamplifier circuit is formed by a current mirror circuit. That is, aconstant voltage VR is applied across the gate and the source of aMOSFET Q11 to form a constant current which is allowed to flow into adiode-connected P-channel MOSFET Q12. The gate of the MOSFET Q12 and thesource of the MOSFET Q9 are connected in common to constitute a currentmirror circuit, and the constant current is permitted to flow into theMOSFET Q9.

The MOSFET Q12 is provided with a MOSFET Q13 in the form of a currentmirror which is connected to a diode-connected N-channel MOSFET Q14. Thegate of the MOSFET Q14 and the source of the MOSFET Q10 are connected incommon to constitute a current mirror circuit, and the above-mentionedconstant current is permitted to flow into the MOSFET Q10. Theconstitution in other respects is the same as that of the embodiment ofFIG. 1, and is not described.

In this embodiment, the operation current of the amplifier circuit isformed based upon a constant current obtained based upon the constantvoltage VR. Therefore, the current that flows into the amplifier circuitis stabilized, and a desired level-shifting operation is stably carriedout.

FIG. 5 is a block diagram illustrating a portion of an embodiment of apreferred digital signal processor according to the present invention.The digital signal processor of this embodiment is included in anoverall digital communication network, i.e., in an ATK (asynchronoustransfer mode) switch-board of ISDN (integrated services digital networksystem). Though there is no particular limitation, the digital signalprocessor includes many electronic circuit packages mounted on one or aplurality of racks, and a plurality of semiconductor integrated circuitdevices (LSIs) mounted on these electronic circuit packages areconnected together via a transmission line. Though the symbols attachedto the MOSFETs constituting the signal receiving circuit UBR are partlyoverlapping those of FIG. 1 or 2, it should be noted that these elementshave separate circuit functions.

Though there is no particular limitation in this embodiment, theelectronic circuit package constituting the digital signal processor isfabricated based upon a CMOS or bipolar CMOS circuit or a false ECLcircuit to meet the required functions. That is, when the operationspeed is not required, a high degree of integration and decreased powerconsumption are realized by using the CMOS circuit. When an intermediatedegree of speed is required, the bipolar CMOS circuit is used and when ahigh-speed operation is required, the false ECL circuit is used. Bycombining a variety of semiconductor integrated circuit devices to meetthe individual circuit functions, the digital signal processor as awhole features a high-speed operation, a high degree of integration anda decreased power consumption.

FIG. 5 representatively illustrate a transmitter circuit UBD and areceiving circuit IBR in two large-scale integrated circuit devicesVLSI11 and VLSI12 in an electronic circuit package constituting thedigital signal processor. That is, there are shown a unit transmittercircuit UBD in a signal transmitter circuit BD mounted on thelarge-scale integrated circuit device VLSI11 and a unit receivingcircuit UBR in a signal receiving circuit BR mounted on the large-scaleintegrated circuit device VLSI12.

The large-scale integrated circuit device VLSI11 comprises the signaltransmitter circuit BD made up of a plurality of unit transmissioncircuits UBD, a signal processing circuit (not shown) and, as required,the following signal receiving circuit for receiving signals from otherlarge-scale integrated circuit devices. The large-scale integratedcircuit device VLSI12 comprises the signal receiving circuit BR made upof a plurality of unit receiving circuits UBR, a signal processingcircuit (not shown) and, as required, the above-mentioned signaltransmitter circuit for transmitting signals to other large-scaleintegrated circuit devices.

The unit transmitter circuit UBD provided in the large-scale integratedcircuit device LSI11 is constituted by a transmission buffer BUF forreceiving a signal do0 formed by an internal circuit. The internalsignal do0 is formed by a logic circuit such as the CMOS or bipolar CMOScircuit or false ECL circuit, and assumes a signal level correspondingto the circuit. The transmission buffer BUF outputs, from an output noden1, an output signal corresponding to the internal signal do0 andoutputs, from an output node n2, a signal having a phase oppositethereto.

A pair of signals from the output nodes n1 and n2 are transmitted toinput nodes n3 and n4 of the large-scale integrated circuit device LSI12through a pair of signal transmission lines. In the above-mentioned GTLinterface, the unit transmission circuit UBD is constituted by anopen-drain output MOSFET which, when activated, executes complementaryswitching operation for the signal do0. Terminal resistors are connectedbetween the terminals of the two signal transmission lines and theterminal voltage to be in match with the impedance of the transmissionlines. When the output interface is the false ECL circuit, a signal of afalse ECL level is output. To accomplish high-speed operation and lowpower consumption, the signal levels transmitted through the signaltransmission lines are transformed into small signals as exemplified inFIG. 4.

The unit receiving circuit UBR provided in the large-scale integratedcircuit device LSI12 is constituted by a level-shifting circuit LS and asense amplifier SA which utilizes a differential amplifier circuit forreceiving level-shifted outputs n5 and n6 as shown in FIG. 1. Thelevel-shifting circuit LS was described above in detail with referenceto FIG. 1, and is not described here again. The level-shifting circuitLS works to automatically bring small input signals lying over a widerange into a narrow voltage range of from about 1 V to about 2.5 V.

Since the level-shifted outputs n5 and n6 are within a voltage range offrom about 1 V to about 2.5 V as described above, the sense amplifier SAis formed of N-channel differential MOSFETs Q10, Q11, P-channel loadMOSFETs Q12, Q13 in the form of a current mirror, and current-sourceMOSFET Q14 connected to common sources of the N-channel differentialMOSFETs Q10, Q11 having such sizes that the sensitivity becomes amaximum within the above-mentioned voltage range.

The sense amplifier SA amplifies the level-shifted input signals andoutputs, from an output node n7, output signals of a high level and alow level nearly corresponding to the operation voltage. With adifferential signal being input, no reference voltage is required.Besides, the sense amplifier SA is little affected by fluctuation in theprocessing, since properties of a pair of differential elements formedin the integrated circuit have similarly been fluctuated through theproduction processing, and is capable of canceling common-mode noise andmaintains sufficient degree of operation margin. The output signal ofthe sense amplifier SA is taken by an internal circuit that is not shownas a reception signal di0 having a CMOS level through the output bufferB1.

In this embodiment, the level-shifting circuit LS is provided with apower switch MOSFET which is controlled by a control signal φpr togetherwith the current-source MOSFET Q14 in the sense amplifier SA so that nodirect current will be wasted in the modes other than the signalreception mode. That is, with the signal φpr being set to the low level,the power switch MOSFET in the level-shifting circuit LS and thecurrent-source MOSFET Q14 in the sense amplifier are turned off toprevent current from flowing in these circuits.

In order that the output signal of the sense amplifier SA will notassume an indefinite level when it is not in operation, a P-channelMOSFET Q15 is provided between the output node n7 of the sense amplifierSA and the power-source voltage VDD, and the control signal φpr is fedto the gate thereof. When the sense amplifier SA is not in operation,therefore, the P-channel MOSFET Q15 is turned on, and the output node n7of the sense amplifier SA is forcibly set to the high level. When thesense amplifier SA is not in operation, therefore, the reception signaldi0 output through the output buffer B1 is set to the high level.

When the internal circuit of the semiconductor integrated circuit deviceLSI12 is constituted by the false ECL circuit, the output buffer B1 isprovided with a level conversion function for conversion into a falseECL level. Or, the level may be converted into the false ECL level afterit has been converted into the CMOS level by the CMOS inverter circuit.As described above, the output signal of the sense amplifier SA isconverted for its level so as to be adapted to the logic form of theinternal circuit in the semiconductor integrated circuit device on whichthe sense amplifier SA is mounted.

FIG. 6 is a diagram of waveforms for explaining the operation of thecircuit of FIG. 5. On the transmission side, small signals that changecomplementarily appear at the output nodes n1 and n2 depending upon thehigh level and the low level of the internal signals do0. The signalsare transmitted at low levels that change on the side of thepower-source voltage VDD such as the false ECL level or the ALTS levelas shown in FIG. 4.

On the receiving side, the control signal φpr has the high level, andthe level-shifting circuit LS and the sense amplifier SA are inoperation. In the level-shifting circuit LS, a low level such as ALTSdeviated toward the side of the power-source voltage VDD is shifted tonear the intermediate voltage like VDD/2, and is shifted for its levelmaintaining a small amplitude such as +0.1 V and -0.1 V about VDD/2. Thesense amplifier SA amplifies the level-shifted small signal and forms,through the output buffer B1, a reception signal di0 of the CMOS levelhaving a high level such as the power-source voltage VDD and a low levelsuch as ground potential VSS of the circuit.

When the receiving operation is finished on the receiving side, thecontrol signal φpr assumes the low level. This interrupts the operationcurrent of the level-shifting circuit LS and the sense amplifier SA, andcauses the P-channel MOSFET at the output portion of the sense amplifierSA to be turned on, so that the output signal is fixed to the highlevel. Therefore, the output signal di0 of the output buffer B1 assumesthe high level, too.

FIG. 7 is a block diagram schematically illustrating an embodiment of adigital data processing system according to the present invention. Inthis embodiment, three large-scale integrated circuits LSI1 to LSI3 arerepresentatively shown.

The large-scale integrated circuit LSI1 processes the digital signalsthrough a false ECL circuit. Therefore, an output signal of the falseECL level is transmitted as a transmission signal from the large-scaleintegrated circuit LSI1 to the large-scale integrated circuit LSI3. Thelarge-scale integrated circuit LSI3 processes the digital signalsthrough the CMOS circuit. Therefore, a bias-free receiving circuit usingthe signal receiving circuit of the present invention effects theconversion into the reception signal and the CMOS level.

The large-scale integrated circuit LSI2 processes the digital signalsthrough the CMOS circuit. However, the signal is output to thelarge-scale integrated circuit LSI1 from the GTL circuit. Accordingly,the above-mentioned bias-free circuit is used as the receiving circuitin the large-scale integrated circuit LSI1, and a level convertercircuit is provided at the output portion to convert the level into thefalse ECL level. The GTL signal formed by the large-scale integratedcircuit LSI1 is also transmitted to the large-scale integrated circuitLSI3. The large-scale integrated circuit LSI3 processes the digitalsignals through the same CMOS circuit as that of the large-scaleintegrated circuit LSI2 but has different output interfaces like GTL andALTS. In order to exchange the signals between the large-scaleintegrated circuits LSI2 and LSI3, therefore, the transmission andreception are effected at different signal levels by using the bias-freecircuit.

When the digital signal processing is effected by using the same CMOScircuit or the bipolar CMOS circuit, it is desired that the circuit isuniformized like GTL or ALTS. For this purpose, however, the large-scaleintegrated circuit must be designed to meet the individual interfaces.According to the present invention, the receiving circuit includes theabove-mentioned bias-free circuit making it possible to exchange signalsto and from large-scale integrated circuits having any signal level.Therefore, an integrated circuit can be newly designed and developed tomeet the functions; i.e., the existing semiconductor integrated circuitshaving particular low-amplitude interfaces can be resultant together toconstitute a digital signal processing system. This makes it possible toenhance the efficiency for mass-producing the semiconductor integratedcircuit devices having a variety of low-amplitude interfaces and to forman ideal digital signal processing system.

FIG. 8 is a circuit diagram illustrating another embodiment of the senseamplifier used for the signal receiving circuit according to the presentinvention. This embodiment employs a double-balanced differential senseamplifier in order to increase the gain for the small input signals likeALTS. That is, by using two single-ended differential sense amplifiersas shown in FIG. 5, the input signals IN1 and IN2 are so supplied thatthe output signals will have phases opposite to each other, andcomplementary output signals of the two single-ended differential senseamplifiers are fed to a differential amplifier circuit in the outputstage.

In order to prevent a direct current from flowing into the senseamplifier in the modes other than the signal reception mode, thecurrent-source MOSFET for forming an operation current in eachdifferential circuit is turned off by the control signal φpr. In thiscase, in order to prevent the output signal from assuming an indefinitelevel, the output unit is provided with the P-channel MOSFET which iscontrolled by the control signal φpr to fix the output node to the highlevel.

Described below are the actions and effects exhibited by theabove-mentioned embodiment.

The invention employs a first P-channel amplifier MOSFET and a firstN-channel amplifier MOSFET having gates supplied with positive signalsfrom a pair of signal transmission lines, and a second P-channel MOSFETamplifier and a second N-channel MOSFET amplifier having gates suppliedwith negative signals from said pair of signal transmission lines, andforms a first output signal by so adjusting the gains of the firstP-channel MOSFET amplifier and of the second N-channel MOSFET amplifierthat the resultant signals have an intermediate amplitude between theoperation voltages, and forms a second output signal by so adjusting thegains of the second P-channel MOSFET amplifier and of the firstN-channel MOSFET amplifier that the resultant signals have anintermediate amplitude between the operation voltages, making itpossible to receive various small signals lying over a wide range evenby using a sense amplifier which has only a fixed operation range.

Moreover, complementary digital output signals having different levelsare sent onto a pair of first and second signal transmission lines andare received by a first (second) receiving circuit which comprises afirst (third) P-channel MOSFET amplifier and a first (third) N-channelMOSFET amplifier having gates supplied with positive signals; a second(fourth) P-channel MOSFET amplifier and a second (fourth) N-channelMOSFET amplifier having gate supplied with negative signals, said first(second) receiving circuit forming a first (third) output signal by soadjusting the gains of the first (third) P-channel MOSFET amplifier andof the second (fourth) N-channel MOSFET amplifier that the resultantsignals have an intermediate amplitude between the operation voltagesand forming a second (fourth) output signal by so adjusting the gains ofsaid second (fourth) P-channel MOSFET amplifier and a first (third)N-channel MOSFET amplifier that the resultant signals have anintermediate amplitude between the operation voltages, making itpossible to constitute a novel and optimum system by combiningsemiconductor integrated circuit devices having different low-amplitudeinterfaces.

A first output signal and a second output signal of the signal receivingcircuit are fed to a differential sense amplifier and are converted intodigital signals. Therefore, common-mode noise is canceled withoutrequiring a reference voltage, making it possible to maintain asufficiently large operation margin.

By using the signal receiving circuit for the input circuit of thedigital integrated circuit, it is allowed to form a semiconductorintegrated circuit device that can be adapted to a variety oflow-amplitude interfaces, contributing to enhancing the mass-productionefficiency.

The low-amplitude interfaces may take a variety of forms. The signalreceiving circuit is mounted on a large-scale integrated circuit or may,by itself, be constituted by a semiconductor integrated circuit device.In the CMOS integrated circuit, for instance, efforts have been made tolower the operation voltage to be about 3 V. In the existing CMOScircuits or the false ECL circuits, on the other hand, use is made of apower-source voltage of 5 V. Hence, the receiving circuit must use avoltage which is relatively as large as 5 V. Therefore, the signalreceiving circuit may be fabricated as a semiconductor integratedcircuit device that operates on 5 V and may be used as a buffer, inorder to feed the output signal to a semiconductor integrated circuitdevice which operates on a law voltage such as 3 V.

When the receiving circuit is mounted on a large-scale integratedcircuit and when the internal circuit must be operated on a low voltagesuch as 3 V, the internal circuit may include a voltage-lowering circuitto lower the voltage of the internal CMOS circuit down to about 3 V,while receiving 5 V from an external unit. Or, two power-sourcevoltages, e.g., 5 V and about 3 V may be supplied through the externalterminals. In an integrated circuit of the bipolar CMOS constitution,the output element of the GTL interface may be a bipolar transistor. Theload MOSFET used for the level-shifting circuit may be replaced by aresistor element.

The large-scale integrated circuit may be provided with a signaltransmitter circuit and a signal receiving circuit. That is, alarge-scale integrated circuit is constituted for each of the functionalblocks, and the signal receiving circuit of the invention is utilizedfor transmitting the signals among the blocks.

Industrial Applicability

As described above, the signal receiving circuit and the digital signalprocessing system of the present invention can be extensively used for avariety of signal receiving circuits and digital signal processingsystems such as digital switch-board systems, high-speed computers, etc.

We claim:
 1. A signal receiving circuit comprising:a first P-channelMOSFET amplifier and a first N-channel MOSFET amplifier having gatessupplied with positive signals from a pair of signal transmission lines;and a second P-channel amplifier MOSFET and a second N-channel MOSFETamplifier having gates supplied with negative signals from said pair ofsignal transmission lines; wherein a first output signal is formed bycommonly using the outputs of the first P-channel MOSFET amplifier andof the second N-channel MOSFET amplifier and by so adjusting the gainsthereof that the resultant signals have an intermediate amplitudebetween the operation voltages; and a second output signal is formed bycommonly using the outputs of the second P-channel MOSFET amplifier andof the first N-channel MOSFET amplifier and by so adjusting the gainsthereof that the resultant signals have an intermediate amplitudebetween the operation voltages.
 2. A signal receiving circuit accordingto claim 1, wherein the first output signal and the second output signalof said signal receiving circuit are fed to a differential senseamplifier and are converted into digital signals.
 3. A signal receivingcircuit according to claim 1, wherein said signal receiving circuit isused for an input circuit of a digital integrated circuit.
 4. A signalreceiving circuit according to claim 2, wherein said signal receivingcircuit is used for an input circuit of a digital integrated circuit. 5.A digital signal processing system comprising:first and secondsemiconductor integrated circuit devices each including a signaltransmission circuit that sends complementary digital output signals ofdifferent levels onto a pair of first and second signal transmissionlines; and a third semiconductor integrated circuit device comprising:afirst signal receiving circuit which includes:a first P-channel MOSFETamplifier and a first N-channel MOSFET amplifier having gates suppliedwith positive signals from said pair of first signal transmission lines;and a second P-channel MOSFET amplifier and a second N-channel MOSFETamplifier having gates supplied with negative signals from said pair offirst signal transmission lines; said first signal receiving circuitforming a first output signal by commonly using the outputs of the firstP-channel MOSFET amplifier and of the second N-channel MOSFET amplifierand by so adjusting the gains thereof that the resultant signals have anintermediate amplitude between the operation voltages, and a secondoutput signal by commonly using the outputs of the second P-channelMOSFET amplifier and of the first N-channel MOSFET amplifier and by soadjusting the gains thereof that the resultant signals have anintermediate amplitude between the operation voltages; a firstdifferential sense amplifier which receives the output signals from saidsignal receiving circuit and converts them into digital signals; asecond signal receiving circuit which includes:a third P-channel MOSFETamplifier and a third N-channel MOSFET amplifier having gates suppliedwith positive signals from said pair of second signal transmissionlines; and a fourth P-channel MOSFET amplifier and a fourth N-channelMOSFET amplifier having gates supplied with negative signals from saidpair of second signal transmission lines; said second signal receivingcircuit forming a third output signal by commonly using the outputs ofthe third P-channel MOSFET amplifier and of the fourth N-channel MOSFETamplifier and by so adjusting the gains thereof that the resultantsignals have an intermediate amplitude between the operation voltages,and a fourth output signal by commonly using the outputs of the fourthP-channel MOSFET amplifier and of the third N-channel MOSFET amplifierand by so adjusting the gains thereof that the resultant signals have anintermediate amplitude between the operation voltages; and a seconddifferential sense amplifier which receives the output signals from saidsignal receiving circuit and converts them into digital signals.
 6. Adigital signal processing system according to claim 5, wherein saidfirst and second semiconductor integrated circuit devices includeinternal logic circuits of different types.